Hybrid phase locked loop having wide locking range

ABSTRACT

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Indian Patent Application No.962/MUM/2015, filed Mar. 23, 2015, the contents of which areincorporated in this disclosure by reference in their entirety.

BACKGROUND

Prior art phased lock loops (PLLs) use measurement of the phasedifference between a reference signal and the feedback signal, afterfrequency division, to adjust the frequency of a digitally controlledoscillator that generates the feedback signal. A frequency division canbe employed in the reference signal and/or the feedback signal beforeprior to phase error measurement.

A digital phase locked loop (DPLL) in general comprises a phasecomparator, a loop filter, a digital controlled oscillator, and afeedback path. The feedback signal is compared with a reference signalto generate an error signal. The loop filter filters the error signal togenerate the control signal for the digital controlled oscillator. Inthis way the output of the phase locked loop is locked to the referencesignal. The convergence time is the time it takes for the output to lockon to the reference signal and is proportional to the filter bandwidth.A low filter bandwidth is desirable to reduce jitter but this implies along convergence time.

In one type of DPLL, known as a type II PLL, the loop filter is ofsecond order. The loop filter has two parts, known as the proportionalor P-part, and integral I-part, which generate corresponding componentsof the DCO frequency control signal. The I-part accumulates the phaseerrors into a frequency offset, which is added to the instantaneousphase from the P-part in each cycle. The convergence time is normallydominated by the P-part. However, when the frequency is in lock with thereference signal and the I-part has a small frequency offset, theresidual phase convergence time is governed by the small error from theI-part. Under these circumstances the phase error can be correctedextremely slowly, especially when the loop bandwidth is low.

A typical type II DPLL 10, shown in FIG. 1, comprises a phase comparator12 to measure phase error, a loop filter 14, and a digital controlledoscillator (DCO) 16. The phase comparator 12 compares the phase of areference clock Φref (or a reference clock divided by 1/M in frequencydivider 18) and the output of the local DCO 16 or some derivativethereof, for example, a fraction thereof (through frequency divider 20),potentially with some preset offset, with the phase error Φerr being theoutput of phase comparator 12. It will be understood that the DPLL 10operates under the control of a system clock (not shown).

A typical loop filter 14 includes a proportional (P) component 22 and anintegral (I) component 24, as shown in FIG. 2. In the proportional (P)component 22 of loop filter 14, multiplier 26 multiplies the output Φerrof a phase comparator used as the phase error measurement element 12 bythe scaling factor K_(P). The output of multiplier 26 is provided to theintegral (I) component 24 including multiplier 28 having the integralfactor K_(I) as an input. An integrator consisting of adder 30 andmemory 32 with a unit delay forms part of a delayed feedback loop. Themultiplier 26 produces a phase compensation component dfp and themultiplier 28 and integrator (adder 30 and memory 32) produce anintegral component dfi, representing a frequency offset relative to thefrequency of the reference clock Φref. The components dfp and dfi arefurther summed in adder 34 to produce a control signal df which isarranged to set the frequency of the DCO 16 of FIG. 1 so that it becomeslocked to the reference clock Φref.

The memory 32 stores the value of the frequency component dfi for onecycle so that the current inputs to the adder 30 are (previous cycledfi)+K_(I)*dfp (current cycle). Consequently the DCO control signal dfat the output of the adder 34 is given by df=dfp (current cycle)+dfi(previous cycle)+K_(I)*dfP (current cycle).

The loop bandwidth is generally set by user and is determined by thescaling factor K_(P), which is typically set to be: K_(P)=2πf/fsys,where f is the loop bandwidth and fsys is the system clock frequency forthe DPLL 10. The multiplier 26 will give an instantaneous PLL updatevalue dfp, since there is no memory component. The integral factorK_(I), which is input to the multiplier 28, maintains the filterintegral part at a very low rate in relation to the instantaneous PLLupdate value dfp and in general: K_(I)=K_(P)/D, where D>>1 is a dampingfactor.

When phase difference is the only variable considered when correctingthe frequency of the DCO, the locking range of the PLL is limited by theloop bandwidth. To increase the locking range the loop gain has to beincreased which in turn increases the frequency noise in the output.

Therefore, there is a need for a new way to control a PLL which is notassociated with these disadvantages.

SUMMARY

The present invention provides a method to increase the locking range ofa PLL by providing an additional variable for frequency correction. Thepresent invention measures the frequency difference between thereference signal and the feedback signal and uses an additional controlloop to force the frequency difference to zero. The frequency differenceis derived from phase error measurement. The frequency error is forcedto zero by using an additional closed loop controller which can be assimple as a PI controller or a complex algorithm-based controller. Byusing the proposed method, the locking range of the PLL can be increasedwithout increasing the loop gain of phase error based frequencyadjustment.

According to one embodiment of the present invention, a digital phasedlocked loop includes a digital controlled oscillator configured toproduce an output signal at a frequency. A phase comparator compares theoutput signal, or a signal derived therefrom, with a reference signal toproduce a phase error signal. A first loop filter produces a firstcontrol signal for the digital controlled oscillator from an output ofthe phase comparator. A frequency error measuring circuit coupled to theoutput of the phase comparator produces a frequency error signal. Asecond loop filter produces a second control signal for the digitalcontrolled oscillator from an output of the frequency error measuringcircuit. A circuit combines the first and second control signals andprovides the combined control signals to the digital controlledoscillator.

DRAWINGS

These and other features, aspects and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings where:

FIG. 1 is a block diagram of a typical prior-art DPLL;

FIG. 2 is a block diagram of a typical loop filter used in the phasecorrection loop of a DPLL of the prior art;

FIG. 3 is a block diagram of a phase locked loop in accordance with theprinciples of the present invention;

FIG. 4 is a diagram of the DPLL of FIG. 3, showing the loop filters inmore detail;

FIGS. 5A, 5B, and 5C are diagrams explaining the measurement offrequency from phase in accordance with one aspect of the presentinvention.

DESCRIPTION

Persons of ordinary skill in the art will realize that the followingdescription of the present invention is illustrative only and not in anyway limiting. Other embodiments of the invention will readily suggestthemselves to such skilled persons.

A particular embodiment of the present invention is shown in FIG. 3, ablock diagram of an illustrative DPLL 40 in accordance with theprinciples of the present invention. Certain ones of the components ofDPLL 40 are similar in form and function to components in the prior-artDPLL 10 depicted in FIG. 1. These components will be referred to usingthe same reference numerals used to designate their counterparts in FIG.1.

DPLL 40 includes a phase comparator 12, a phase loop filter 14, and adigital controlled oscillator (DCO) 16. Phase comparator 12 compares thephase of a reference clock Φref (or a reference clock divided by 1/M infrequency divider 18) and the output of the local DCO 16 or somederivative thereof, for example, a fraction thereof (through 1/Nfrequency divider 20), potentially with some preset offset, with thephase error Φerr being the output of phase comparator 12. It will beunderstood that the whole circuit operates under the control of a systemclock (not shown).

Phase loop filter 14 includes a P component 14-22 and I component 14-24similar to those depicted in FIG. 2, or any other prior art DPLLarrangement, including the DPLL taught in U.S. Pat. No. 6,236,343 issuedMay 22, 2001 to Patapoutian, entitled “Loop Latency Compensated PLLFilter”, the entire contents of which is incorporated herein byreference. Irrespective of arrangement, the output of phase loop filter14 comprises a signal which in the prior art is fed to DCO 16 to lockthe output of DCO 16 to the reference signal.

Referring now to FIG. 4, in the P component of phase loop filter 14,multiplier 14-26 multiplies the output Φerr of the phase comparator thatcomprises phase error measurement element 12 by the scaling factorK_(P). The phase error signal Φerr is further provided to the Icomponent 14-24 including multiplier 14-28 having the integral factorK_(I) as an input. An integrator consisting of adder 14-30 and memory14-32 with a unit delay forms part of a delayed feedback loop. Themultiplier 14-26 produces a phase compensation component dfp_(a) and themultiplier 14-28 and integrator (adder 14-30 and memory 14-32) producean integral component dfi_(a), representing a phase offset relative tothe reference clock Φref. The components dfp_(a) and dfi_(a) are furthersummed in adder 14-34 to produce a first control signal df_(a) which isarranged to set the frequency of the DCO 14 so that it becomes locked inphase to the reference clock Φref.

The memory 14-32 stores the value of the frequency component dfi_(a) forone cycle so that the current input dfi_(a) to the adder 14-34 is(previous cycle dfi_(a))+K_(I)*dfp_(a) (current cycle). Consequently thefirst control signal dfa at the output of the adder 14-34 is given bydf_(a)=dfp_(a) (current cycle)+dfi_(a) (previous cycle)+K_(I)*dfp_(a)(current cycle).

The loop bandwidth for phase loop filter 14 is generally set by user andis determined by the scaling factor K_(P), which is typically set to be:K_(P)=2πf/fsys, where f is the phase loop bandwidth and fsys is thesystem clock for the DPLL phase loop. The multiplier 14-22 will give aninstantaneous PLL update value dfp. The scaling factor K_(I), which isinput to the multiplier 14-28, maintains the filter integral part at avery low rate in relation to the instantaneous PLL update value dfp_(a)and in general: K_(I)=K_(P)/D, where D>>1 is a damping factor.

According to one aspect of the present invention, a second control loopfor the DPLL 40 including frequency error measurement element 42 andfrequency loop filter 44 corrects for frequency offset. Adder 46combines the outputs of loop filter 16 and loop filter 42. The secondcontrol loop cooperates to improve locking when the frequency differenceis larger than the phase loop bandwidth.

Frequency loop filter 44 includes a P component 44-22 and I component44-24 similar to those of phase loop filter 14. In the P component offrequency loop filter 44, multiplier 44-26 multiplies the output of thefrequency error measurement 42 by the scaling factor K_(P). Thefrequency error signal is provided to the I component 44-24 includingmultiplier 44-28 having the integral factor K_(I) as an input. Anintegrator consisting of adder 44-30 and memory 44-32 with a unit delayforms part of a delayed feedback loop. The multiplier 44-26 produces afrequency compensation component dfp_(b) and the multiplier 44-28 andintegrator (adder 44-30 and memory 44-32) produce an integral componentdfi_(b), representing a frequency offset relative to the frequency ofthe reference clock Φref. The components dfp_(b) and dfi_(b) are furthersummed in adder 44-34 to produce a second control signal df_(b) which isarranged to set the frequency of the DCO 14 so that it becomes locked tothe reference clock Φref.

The memory 44-32 stores the value of the frequency component dfi_(b) forone cycle so that the current input dfi_(b) to the adder 44-34 is(previous cycle dfi_(b))+K_(I)*dfp_(b) (current cycle). Consequently thesecond control signal df_(b) at the output of the adder 44-34 is givenby df_(b)=dfp_(b) (current cycle)+dfi_(b) (previous cycle)+K_(I)*dfp_(b)(current cycle).

The loop bandwidth for frequency loop filter 44 is generally set by userand is determined by the integral factor K_(I)p. The multiplier 44-26will give an instantaneous PLL update value dfp. The integral factorK_(I), which is input to the multiplier 44-28, maintains the filterintegral part at a very low rate in relation to the instantaneous PLLupdate value dfp and in general: K_(I)=K_(P)/D, where D>>1 is a dampingfactor.

The outputs of phase loop filter 14 and frequency loop filter 44 aresummed in adder 46, to provide a combined control signal for DCO 14. Theaddition of second control signal dfb from frequency loop filter 44allows the system to lock over a wider frequency range than would bepossible if only phase loop filter 14 was used.

Referring now to FIGS. 5A, 5B, and 5C, diagrams explain the measurementof frequency from phase in accordance with one aspect of the presentinvention, as performed by frequency error measurement element 42. Theupper trace in both FIGS. 5A and 5B show the reference frequency signaland the DCO output signal superimposed, the reference signal being thetrace shown lower on the y-axis in the upper portions of FIGS. 5A and5B. The lower of the two superimposed traces in both FIGS. 5A and 5Bshows the phase difference between the reference frequency signal andthe DCO output signal.

The phase difference between the reference signal and the feedbacksignal from the DCO is measured by counting the number of system clockcycles between the rising edge of the reference signal and the risingedge of the feedback signal. The measurement is performed after theoptional frequency dividers 18 and 20. The phase difference measuredthis way has a different pattern when the feedback signal frequency islower than that of reference signal (FIG. 5A) and when feedback signalfrequency is higher than that of reference signal (FIG. 5B).

The periodicity of phase difference (number of cycles per second)directly represents the frequency difference between the reference clocksignal Φref and the feedback signal. The frequency difference can becomputed by measuring T as shown in FIG. 5A and calculating 1/T. Thisprocess involves a division which is resource and time consuming.

The frequency difference can also be found by counting the number ofphase transitions in a fixed time window as shown in FIG. 5C. If themeasuring window is 10 milliseconds and number of phase transitions are8 then the frequency is 8/0.01=800, where 1/0.01 is a fixed factor andhence division is not required because both numerator and denominatorcan be multiplied by a number that makes the denominator equal to 1.

One way to find if the frequency difference is positive or negative isto find the difference between the present value of phase difference andthe most immediately previous value of phase difference. If thedifference is positive (except at transitions where difference value istoo large and is not considered) then the frequency difference ispositive. If the difference is negative, then the frequency differenceis negative.

The addition of a loop filter for frequency raises the challenge oftuning two closed loop controllers to control a single system. However,by properly tuning the loop filters of the phase loop and the frequencyloops the locking range of the PLL is increased by many times comparedto the PLL of the prior art. The phase loop is preferably tuned suchthat the locking frequency range of the phase loop is equal to, orgreater than, the frequency resolution (minimum frequency change thatcan be measured) of the error measurement element 42. Also the dynamicresponse of the frequency loop filter 44 should be slower than that ofphase loop filter 14. The integrator in the frequency loop filter 44plays a major role in defining its dynamics.

Although the present invention has been discussed in considerable detailwith reference to certain preferred embodiments, other embodiments arepossible. Therefore, the scope of the appended claims should not belimited to the description of preferred embodiments contained in thisdisclosure.

What is claimed is:
 1. A digital phased lock loop comprising: a digitalcontrolled oscillator configured to produce an output signal at afrequency; a phase comparator configured to compare the output signal,or a signal derived therefrom, with a reference signal to produce aphase error signal; a first loop filter configured to produce a firstcontrol signal for the digital controlled oscillator from an output ofthe phase comparator; a frequency error measuring circuit coupled to theoutput of the phase comparator and configured to produce a frequencyerror signal; a second loop filter configured to produce a secondcontrol signal for the digital controlled oscillator from an output ofthe frequency error measuring circuit; and a circuit for combining thefirst and second control signals and providing the combined controlsignals to the digital controlled oscillator.
 2. The digital phased lockloop of claim 1, wherein: the first loop filter comprises a proportionalpart producing a proportional component of the control signal, anintegral part producing an integral component of the control signal, andan adder configured to receive the respective proportional and integralcomponents at first and second inputs thereof to produce the controlsignal, the integral part including a delayed feedback loop normallyconfigured to accept the integral component at an input thereof; and thesecond loop filter comprises a proportional part producing aproportional component of the control signal, an integral part producingan integral component of the control signal, and an adder configured toreceive the respective proportional and integral components at first andsecond inputs thereof to produce the control signal, the integral partincluding a delayed feedback loop normally configured to accept theintegral component at an input thereof.
 3. The digital phase locked loopof claim 1, wherein: the delayed feedback loop in the first and secondloop filters each comprise a unit delay memory.
 4. The digital phaselocked loop of claim 1, wherein: the frequency error measuring circuitis configured to count the number of phase transitions in a fixed timewindow and determined the frequency error responsive to said countednumber of phase transitions.
 5. The digital phase locked loop of claim1, wherein: the frequency error measuring circuit is configured todetermine the periodicity of the phase difference between the outputsignal and the reference signal and compute the inverse of thedetermined periodicity to measure the frequency error.
 6. A method ofreducing the convergence time in a digital phase locked loop,comprising: comparing the phase of an output signal, or a signal derivedtherefrom, of a digital controlled oscillator, the output signal havingphase and frequency with a reference signal to produce a phase errorsignal; filtering the phase error signal in a first loop filter having aproportional part producing a proportional component and an integralpart producing an integral component, the integral part including adelayed feedback loop normally receiving at an input thereof theintegral component; applying the proportional and integral components torespective first and second inputs of an adder to produce a firstcontrol signal; comparing the frequency of the output signal with thefrequency of the reference signal, or a signal derived therefrom toproduce a frequency error signal; filtering the frequency error signalin a second loop filter having a proportional part producing aproportional component and an integral part producing an integralcomponent, the integral part including a delayed feedback loop normallyreceiving at an input thereof the integral component; and combining thefirst and second control signals and providing the combined controlsignals to the digital controlled oscillator.
 7. The method of claim 6wherein comparing the frequency of the output signal with the frequencyof the reference signal, or a signal derived therefrom comprises:counting the number of phase transitions in a fixed time window; anddetermining the frequency error responsive to said counted number ofphase transitions.
 8. The method of claim 6 wherein comparing thefrequency of the output signal with the frequency of the referencesignal, or a signal derived therefrom comprises: determining theperiodicity of the phase difference between the output signal and thereference signal; and computing the inverse of the determinedperiodicity.